Input buffer circuits are well known. Examples of input buffer circuits include single-ended input buffer circuits having transistor-transistor logic (TTL) architecture and differential input buffer circuits having emitter-coupled logic (ECL) or positive ECL (PECL) architecture. Conventional single-ended input buffer circuits and differential input buffer circuits require different designs due to the compatibility of signal levels. For example, the voltage levels of PECL and CML circuits are typically higher than the voltage levels of TTL circuits. Another example is that single-ended signals such as TTL require a switching threshold voltage while differential signals do not require any additional reference voltage.
One problem with existing systems is that differential signals such as PECL or CML are often mixed with single-ended signals such as TTL. Therefore, it is difficult to predict the interface required. Another problem is testing; a user may want to use a single-ended signal for testing while using differential signals during normal operation. One conventional solution is to utilize two different types of input buffer circuits. For example, a system can be designed having both a single-ended input buffer circuit and a differential input buffer circuit. The system would also include a multiplexor to select between the two input buffer circuit types. One problem with this approach is that it requires more space on the chip and requires additional external pins.
Accordingly, what is needed is an improved input buffer circuit that provides flexibility by enabling a user to choose optimal solutions for various applications. The present invention addresses such a need.